Spin Memory’s Endurance Engine is a combination of circuits and design architectures that are wholly implemented in digital circuitry, which means the Endurance Engine can be implemented in any logic or memory digital process. It also is designed to work with any pMTJ. The result: the Endurance Engine will improve any MRAM solution.
Spin Memory’s Endurance Engine enables up to 6 orders of magnitude improvement in endurance while enabling SRAM-like Read and Write speeds. Other MRAMs use Write voltages that guarantee a Write Error Rate (WER) that is low enough to be correctable by 2 bits ECC – typically around 10-9, but require a voltage that will wear-out a device in 106 – 108 cycles – far too short for SRAM or DRAM applications. Spin Memory solves this problem by lowering the Write Voltage so that endurance is greater than 1013 cycles while eliminating the much higher WER. Just like SRAM and DRAM, users will see no errors when using standard 2-bit ECC and the Endurance Engine.
Spin Memory Endurance Engine Benefits:
Enhances speed to 10 ns, depending on pMTJ and CMOS process
Boosts endurance by up to 6 orders of magnitude with no retention change
Works with any pMTJ and any logic or memory digital process
Purely circuit-based with no materials or process changes
No user-visible errors
Spin Memory Teams with Applied Materials to Produce a Comprehensive Embedded MRAM Solution