Careers

Help Create The Future With Spin Memory.

Spin Memory is at the forefront of innovation with our breakthrough MRAM technologies that are enabling the electronics, digital applications and devices of tomorrow. Join our team of world-class magnetics, circuits and memory architect experts and discover what we can do together.

We’re Focused On Your Success.

Based in Fremont, just a few miles east of Silicon Valley, we offer competitive pay, a broad range of benefits and an exciting team-oriented environment. Whether you are working in our fab, designing new technologies or creating new devices, every team member is important as we advance MRAM technologies for high performance, low power applications.

OPEN POSITIONS

MRAM Memory Design Engineer

DESCRIPTION

As a member of our MRAM design team you will develop custom analog circuits for a variety of new MRAM memory devices. You will design, model, and verify critical custom circuits used in our MRAM memory devices. In the design phase, you will also oversee the circuit layout and verify post-layout performance as well as integration into the full chip-level assembly. During design validation, you will drive the analysis of the blocks you designed. This position requires demonstrated custom analog design experience.

QUALIFICATIONS

Candidate should possess a Bachelor or Master of Science degree in Electrical Engineering with 5+ years of directly relevant experience in custom IC circuit design:

  • Significant recent experience with analog design, circuit verification and optimization
  • Experience with layout floor-planning
  • Significant experience with verification of parasitic extractions of the circuits
  • Proficiency performing analog, mixed signal, and co-sim simulations using standard industry simulators
  • Experience with Cadence analog design flow with tools such as Hspice, Spectre, HSIM, Ultrasim, XA
  • Strong communication skills, with the ability to convey complex technical concepts to other design peers in verbal and written form
  • Experience with multi-gigabit CMOS technology
  • Timing generator, bandgap circuit design, current and voltage reference generation, operational amplifier circuits, and sense amplifier circuits experience is a plus
  • Demonstrate a high level of self-motivation

MTJ Structure and Thin Film Materials Engineer

DESCRIPTION

The MTJ Structure Development/Thin Film Materials Development Engineer will be responsible for leading both internal and outsourced layout development activity for logic and MRAM circuitry.

You will be responsible for leading both internal and outsourced layout development activity for logic and MRAM circuitry. You will direct cell, block, and array layout activities for library and full chip projects. Activities will include interfacing with multi-discipline design teams, develop schedule timelines for layout execution and leading your team to implement it, skill development to grow the capabilities of your Physical Design team, developing and implementing methodology improvements to ensure better efficiency and effectiveness, making in-house versus outsource recommendations.

RESPONSIBILITIES

  • Work as an R&D Engineer in the MTJ structure development department
  • Be responsible for developing, characterizing and implementing new MTJ processes and structures for novel MRAM applications
  • Interface and collaborate with other departments within the R&D organization

QUALIFICATIONS

  • M.S./Ph.D. in Physics, Materials Science Engineering, Chemistry or related field
  • Minimum 5 years of relevant experience in magnetic thin film development and characterization
  • Experience in magnetic materials, multilayers and MTJ devices for MRAM applications
  • Hands-on experience in the operation of R&D and Manufacturing types of equipment
  • Hands-on experience in PVD sputtering systems operation and thin film deposition
  • Magnetic thin film characterization techniques: VSM, MOKE, Torque Magnetometer, FMR
  • Physical film analysis techniques such as: SEM, TEM , XPS, XRD, AFM is a plus
  • Able to work in fast paced environment
  • Innovative, detail-oriented and have strong oral and written communication skills
  • Data analysis using JMP, Excel, basic knowledge of Python, LabVIEW is a plus

MRAM Device Characterization Scientist/Device Engineer

DESCRIPTION

As an MRAM Device Characterization Scientist/Engineer you will be part of a highly motivated, dynamic and fast moving team developing spin transfer torque magneto-resistive random access memory (STT-MRAM).

RESPONSIBILITIES

  • Collection and interpretation of electrical and magnetic test data from both individual devices as well as large statistical samples from memory arrays
  • Analysis and evaluation of test data to constantly improve the performance of STT-MRAM devices
  • Reporting and presenting test results to the other teams within the company
  • Development of advanced MRAM characterization techniques to constantly improve test and characterization capabilities
  • Interacting closely with magnetic thin film, device fabrication and chip design teams

QUALIFICATIONS

  • M.S. or Ph.D. in Physics or Electrical Engineering
  • Strong background in solid state physics and devices, with proven expertise in magnetism, MRAM devices, and/or spintronics preferred
  • Significant experience with electrical test and measurement systems
  • Some experience with Labview programming required
  • Strong presentation and communication skills
  • Familiarity with statistical data analysis methods, experience with SAS JMP preferred

Senior Design Verification Engineer

DESCRIPTION

Spin Memory is focused on the development of novel magnetoresistive random access memory (MRAM) technologies and devices in collaboration with New York University researchers and industry partners.  Spin Memory is currently seeking a Senior Design Verification Engineer.

RESPONSIBILITIES

  • Plan and implement Full Chip Functional Verification for Spin Memory’s MRAM Designs
  • Create and maintain test bench for MRAM Memory Devices using System Verilog
  • Develop behavioral models for analog blocks used within Spin Memory’s Memory Devices
  • Identify test coverage measures and provide plan to obtain full test coverage of Memory Devices
  • Work with Design Engineers to provide test benches for Full Chip AMS co-simulations

QUALIFICATIONS

  • BS/MS in Electrical Engineering with 5+ years experience
  • Strong expertise of Verilog
  • Proficient in System Verilog
  • Understanding of Verification Methodologies like UVM
  • Experience building behavioral models of analog blocks, complex logic blocks and memory arrays
  • Proficiency in scripting languages such as TCL, Perl or Python
  • Past experience with IC Design or Memory Design is highly desirable
  • Expertise in using tools such as Synopsys VCS or Cadence Incisive
  • Experience with simulation tools such as AMS, hspice, hsim, ultrasim, AFS, APS, XA

Senior Memory Test Engineer

DESCRIPTION

The Senior Memory Test Engineer is primarily responsible for developing, releasing, improving and maintaining test programs for MRAM devices. This person will work with design, product, process, and device engineering teams to develop and improve test and characterization programs for new products, ensuring products meet quality requirements and development schedules.

QUALIFICATIONS

  • Candidate should possess a Bachelor degree + 8 years of relevant industry experience in a memory test environment
  • A strong knowledge of memory (DRAM /MRAM/ Flash) Test Methodologies, including DFT, DFM, and MBIST
  • Experience working with design engineers to validate operation and performance of memory circuits
  • Experienced in high speed DDR Memory Interface, SRAM, and non-memory devices a plus
  • Knowledge of and familiar with test hardware development for both wafer sort and package level testing
  • Experience in developing characterization programs to characterize devices over process, voltage, and temperature ranges
  • Self-motivated, self-directed with the ability to scope and drive a project independently
  • Ability to work well with others
  • Experience with Nextest (Magnum I/II) ATE platforms is preferred
  • Experience with lab and bench equipment, prober (EG/TSK) and micro probing stations
  • Demonstrated hands-on test and troubleshooting experience
  • Knowledge in Perl, C/ C++ programming language a plus
  • Knowledge in the design of experiments, statistical methods, and data analysis
  • Should have technical background in memory or related technology